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PERTE Chip is one of a series of "Proyectos Estrategicos para la Recuperacion y Transformacion Economica" (PERTE) - cross-ministerial public-private investment programmes funded principally through Spain's allocation of the NextGenerationEU Recovery and Resilience Facility, with national co-funding. The semiconductor PERTE was approved by the Council of Ministers on 24 May 2022, presented by then-First Vice President and Minister for Economic Affairs Nadia Calvino as "probably the most ambitious project of the recovery plan".
The EUR 12.25bn public envelope through 2027 is structured around four lines of action:
1. Reinforcement of scientific capacity (~EUR 1.165bn). R&D for leading-edge microprocessors, alternative architectures, integrated photonics and quantum chips; participation in EU Important Projects of Common European Interest (IPCEI) on microelectronics; co-funding of the Barcelona Supercomputing Center / Intel joint laboratory.
2. Design strategy (~EUR 1.330bn). Fabless design houses, RISC-V alternative-architecture programmes, pilot-line testing, fellowship and training networks aimed at building a domestic design talent pipeline.
3. Manufacturing plant construction (~EUR 9.350bn). The bulk of the envelope - subsidies for front-end fabs at below-5nm and above-5nm nodes, ATMP/OSAT capacity, and supporting cleanroom infrastructure.
4. Dynamisation of ICT/electronics manufacturing (~EUR 0.400bn). Venture fund for semiconductor startups and SMEs and downstream electronics-manufacturing competitiveness measures.
Operationalisation has come through a series of Boletin Oficial del Estado (BOE) instruments, including Orden ETD/856/2023 (PERTE expert group), RD 1131/2023 and RD 714/2024 (cleanroom and microfab subsidies), and Orden ITU/1144/2024 (IPCEI subsidy framework). The Sociedad Espanola para la Transformacion Tecnologica (SETT), a state-owned company constituted by Real Decreto 676/2024 of 16 July 2024, is the formal manager of more than EUR 10.75bn of the PERTE Chip envelope.
comparable to the UK Semiconductor Strategy on a per-capita basis and larger than Italy's chip allocation, but roughly one-quarter of the EU Chips Act mobilisation target and one-fifth of the US CHIPS Act appropriation. Severity 3 reflects meaningful national capex without a market-moving global footprint.
manufacturing line had been slower than envisaged; the Front End of Line (FEOL) call for advanced fab projects has produced no committed greenfield leading-edge fab as yet, and SETT was created only in mid-2024 in part to accelerate that pipeline.
Spanish industrial-policy instrument in the post-2021 EU recovery cycle and the natural anchor for any future Spanish actions (PERTE VEC for EVs, PERTE ERHA for renewables) that may be filed.
the EU Chips Act regulation (18 Sep 2023). It is one of the earliest national-level allied semiconductor subsidy programmes in the post-2021 cycle, framed by the Spanish government as contributing to EU strategic autonomy. Subsequent EU Chips Act IPF/OEF state-aid block exemptions are the legal vehicle relied upon by later PERTE Chip manufacturing-line calls.
utilities, and IPCEI participants), EZU (broader EU semi cluster), SMH/SOXX (incremental European capacity diversifies global fab geography). Named participants include Intel (BSC joint laboratory), STMicroelectronics, Infineon, and NXP.
leading-edge fab anchor tenant before the 2027 NGEU deployment deadline, or will unspent funds be reallocated to design and ATMP?
revision discussions tabled in 2025 by the Commission?
Technologies (ME/CT): which Spanish projects have received IPCEI approval and what is their disbursement status?