Czech Republic National Semiconductor Strategy approved by government

Mechanism

The strategy is a horizontal industrial-policy framework — not a direct subsidy envelope — that aligns Czech state aid, R&D funding, education pipelines and FDI promotion with the EU Chips Act framework. It does not fund a single fab; instead it organises five workstreams (R&D and innovation, talent, exports/investment, business environment, competence centre) around a quantitative scorecard anchored to 2022 baselines.

Czech sector positioning is in the back-end of the European chip stack: power electronics (onsemi Rožnov), IC design houses, and tooling / metrology equipment exporters — rather than leading-edge logic. The strategy explicitly leans into this niche rather than chasing a TSMC- or GlobalFoundries-style fab anchor (the Dresden / Magdeburg plays).

Downstream implications

• First Czech entry in the IPTM register on the western-industrial-policy

axis; complements UK (2023-05-19), Spain PERTE Chip (2022-05-24), Malaysia (2024-05-28), Vietnam Decision 1018 (2024-09-21) and India Semiconductor Mission (2021-12-15) sub-strategies under the EU/ally semiconductor self-reliance umbrella.

• Channels EU Chips Act funding-call participation and IPCEI co-funding

toward Czech-led consortia, particularly in power electronics where onsemi already operates a major SiC fab at Rožnov.

• Workforce target (9,000 specialists by 2029) implies sustained

university-industry programmes and likely tightens labour-market conditions for EE/microelectronics roles in the CEE region.

Open questions

• No state-aid envelope is published in the strategy headline; track the

follow-on MPO calls and any CHIPS-JU contribution announcements.

• Competence centre governance and host institution selection have not

been disclosed publicly as of filing.

• Whether the December 2024 MPO update revised any of the five

quantitative targets — none surfaced in this filing's research pass.