Germany Microelectronics Strategy of the Federal Government — Research, Skilled Labour and Manufacturing for the Microelectronics Ecosystem in Germany

Mechanism

The Microelectronics Strategy is the first cabinet-adopted German microelectronics policy framework since the early 2010s. It is jointly authored by BMFTR (Federal Ministry for Research, Technology and Space) and BMWE (Federal Ministry for Economic Affairs and Energy — formerly BMWK), reflecting the cross-ministerial nature of the chip policy stack in Germany.

The strategy is structured around three pillars:

1. Research — accelerate the development of new chip technologies and shorten the path from research output to production. The strategy leverages the existing Forschungsfabrik Mikroelektronik Deutschland (FMD) network of Fraunhofer, Leibniz and Helmholtz institutes covering the full value chain, and establishes a dedicated competence centre for chip design with an initial flagship project — "supercomputer in the car" — aimed at preparing the automotive and mechanical-engineering industries for AI/HPC-class on-vehicle compute. 2. Skilled Labour — Germany's first targeted federal support programme for the chip-industry talent pipeline. Aims to expand domestic training capacity and attract international specialists. 3. Production — incentives for new semiconductor manufacturing capacity, materials, and systems, anchoring Germany's ~30% share of European wafer capacity and the major fab projects already under way: Intel Magdeburg, Infineon Dresden (Smart Power Fab), TSMC ESMC Dresden, and Wolfspeed Saarland.

Implementation is coordinated by a new Chips Office within the federal government, which is framed in BMFTR/BMWE communications as a "learning strategy" mechanism — i.e., a stakeholder-coordination body rather than a fixed-budget instrument. The fiscal layer is delivered through pre-existing federal vehicles (the [KTF Wirtschaftsplan](2023-08-09-germany-ktf-wirtschaftsplan-2024.md), the EU Chips Act state-aid envelope, and the planned IPCEI "Advanced Semiconductor Technologies" (AST) that BMWE is currently working on with European partners).

The strategy explicitly aligns with the Semicon Declaration signed by all 27 EU member states on 29 September 2025, which called on the European Commission to bring forward a revised EU Chips Act II proposal, expected in Q1 2026.

Downstream implications

• Cement Germany as the EU's anchor wafer-fab jurisdiction. With

~30% of European wafer capacity already in Germany and four major greenfield/brownfield fabs (Intel Magdeburg, TSMC ESMC Dresden, Infineon Dresden, Wolfspeed Saarland), the strategy provides political durability for the multi-year build-out and signals continuity of state-aid support across the legislative cycle.

• Implementation umbrella, not new money. The strategy is a

coordination and signalling instrument — actual subsidy disbursement flows through the KTF, EU Chips Act state-aid approvals, and the planned IPCEI AST. Investors should not double-count this strategy as incremental fiscal commitment beyond what the KTF Wirtschaftsplan and EU Chips Act envelopes already capture.

• Skilled-Labour pillar is the structurally novel element. Unlike

the US CHIPS Act and EU Chips Act, which are primarily capex-subsidy instruments, the German strategy explicitly elevates workforce development to a co-equal pillar — reflecting Germany's binding labour constraint on chip-fab ramp-up (notably visible in the Magdeburg and Dresden fab schedules).

• Sets up EU Chips Act II. Germany's domestic strategy is positioned

as a foundation for the revised EU Chips Act II expected from the Commission in Q1 2026, increasing the probability that the EU-side envelope is materially expanded or restructured around design, packaging, and equipment as well as front-end manufacturing.

Open questions

• No explicit incremental EUR figure was announced — the strategy is

delivered through pre-existing fiscal instruments. Quantitative impact depends on the KTF Wirtschaftsplan trajectory and the IPCEI AST envelope when designed.

• Chips Office governance — the strategy describes a "learning

strategy" coordination body but does not specify its statutory basis, staffing, or budget; this will be visible only in the BMFTR/BMWE follow-on implementation documents.

• Intel Magdeburg slippage risk — if Intel further delays or

cancels the Magdeburg fab, the Production pillar's flagship project is structurally weakened; watch for Intel capex-plan revisions.

• EU Chips Act II proposal scope — Germany has signalled it wants

the revised act to cover design, packaging, and equipment as well as front-end manufacturing; the Commission proposal in Q1 2026 will determine whether Germany's preferences are reflected.