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Base rate computed from analyst-asserted responds_to: edges in the reverse direction (target-country → issuer-country) for prior issuer-actions on the same target. Modal type + lag percentiles only — not a model output. Treat as a historical anchor for sizing counter-response scenarios, not a forecast in itself.
The January 2025 FDD interim final rule (FR doc 2025-00711, published 16 January 2025) established a layered due-diligence regime for foundries and OSATs producing advanced-logic ICs controlled under ECCN 3A090.a. To overcome the rule's red-flag presumption, a fabricator must show that the chip was designed either by an "Approved IC Designer" (BIS-vetted, on a published list) or by an "Authorized IC Designer" (a self-certification pathway available, until the original sunset, to designers headquartered in Country Group A:1 / A:5 or Taiwan and not parented in Macau or D:5).
This 2026-04-09 final rule does two things and only two things:
1. Extends the Authorized IC Designer self-certification pathway from 13 April 2026 to 31 December 2026. 2. Extends the application deadline to become an Approved IC Designer to 31 December 2026, with a 180-day post-deadline "considered authorized" runway for applicants whose review is still pending.
The substantive controls — ECCN 3A090.a thresholds, the foundry / OSAT presumption, License Exception AIA and ACM eligibility, end-user restrictions on Country Group D:5 destinations — are unchanged.
Pure deadline extension. No change in scope, controlled parameters, or eligible destinations. The economic incidence is near-zero on the date of the rule itself; the impact, if any, is to delay the moment when non-Approved Taiwan- and allied-headquartered designers lose the cheap self-certification pathway and must either be on the Approved list or rely on license exceptions / individual licenses.
If anything, the extension reduces near-term compliance friction for TSMC, Samsung Foundry, SK Hynix, and the broader Taiwan / Korea / Japan design ecosystem that is supplying the NVIDIA / AMD advanced-AI accelerator pipeline — which is why we class this as severity 2 (procedural / minor) rather than 1 (clerical).
fab-design firms that had been racing to file Approved IC Designer applications before the original 13 April 2026 cutoff. Reduces the risk of a near-term compliance cliff knocking ICs out of License Exception AIA / ACM eligibility.
signal that BIS is iterating on operational details of the authorized-designer framework rather than rolling it back.
the calendar-year boundary and gives BIS time to publish a more complete Approved IC Designer list before the deadline.
before 31 December 2026? The slow pace of approvals through early 2026 was the practical driver of this extension.
later in 2026 (e.g., tightening of Country Group A:1/A:5 eligibility, or changes to the parent-company test)?
incorporated in A:1/A:5 jurisdictions will be subject to additional scrutiny when the next round of FDD amendments is published.