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Structured register of government actions in the geoeconomic space — export controls, tariffs, sanctions, FDI screening, subsidies, industrial-policy laws — cross-referenced into the country, minerals, and ETF surface. Charter: docs/IPTM_CHARTER.md.
Severity 1-5 is the qualitative impact rating (1=minor, 5=structural). The bilateral-trade-grounded quant scorer is the next IPTM milestone. RBI (Register Breadth Index) is a complementary structural-breadth indicator from scripts/py/iptm/breadth.py; divergence between RBI and severity is itself informative (high-sev / low-RBI = strategic chokepoint; low-sev / high-RBI = broad but shallow). Every action has at least one primary source URL. Verify-or-don't-file. See also themes, timeline, graph, sankey, map, country exposure, sector exposure, material exposure (+ graph), weekly briefs, portfolio scan, escalation monitor, trans-shipment hubs. Internal triage tools (RSS-poller candidate feed, source-feed health) live under /admin/candidates + /admin/sources. Subscribe via Atom feed (accepts ?country=CN, ?material=lithium, ?issuer=BIS, ?type=export_control, ?etf=SOXX, ?company=NVDA, ?minSeverity=4, ?year=2026, ?q=…) or pull /api/iptm/actions.
On 12 March 2026 the UK Cabinet Office (Investment Security Unit) published its Government Response to the consultation on reform of the Notifiable Acquisition Regulations (NARs) under the National Security and Investment Act 2021 — the first major substantive overhaul of the NSI mandatory-notification schedules since the regime took effect on 4 January 2022. The reform splits Critical Minerals out of the existing Advanced Materials schedule into a standalone mandatory schedule covering all 34 minerals on the Critical Minerals Intelligence Centre's latest criticality assessment; splits Semiconductors into its own standalone schedule (capturing advanced packaging and specific chip-design processes); creates a brand-new Water sector schedule covering the 17 regional water and sewerage undertakers in England and Wales; refocuses Artificial Intelligence on entities that create or materially modify AI systems (excluding routine end-use); and refines Communications, Critical Suppliers to Government, Data Infrastructure, Energy and Suppliers to Emergency Services to reduce low-risk capture. An implementing Statutory Instrument is expected later in 2026; the existing NARs remain in force until that SI takes effect.
On 1 February 2026 Finance Minister Nirmala Sitharaman, presenting the Union Budget 2026-27, announced the launch of India Semiconductor Mission (ISM) 2.0 — the second-phase national semiconductor industrial-policy framework succeeding ISM 1.0 (2021, INR 76,000 crore). The Budget makes an initial INR 1,000 crore provision for ISM 2.0 in FY 2026-27 and raises the Electronics Components Manufacturing Scheme (ECMS) outlay from INR 22,919 crore to INR 40,000 crore. ISM 2.0's distinct architecture centres on four strategic priorities not in ISM 1.0: (i) indigenous semiconductor equipment, chemicals, gases and materials production, (ii) full-stack Indian semiconductor IP design, (iii) industry-led R&D and skills/training centres, and (iv) domestic and global supply-chain integration. Total mission outlay reported as approximately INR 1-1.2 lakh crore (~USD 12-14bn) is being finalised; Cabinet clearance and the formal scheme launch are expected by mid-2026.
On 24 December 2025 the Minister of Science and Technology signed Decision No. 4386/QĐ-BKHCN defining the functions, tasks, and organisational structure of the Vietnam National Multi-Project Wafer Coordination Centre (VNMPW/CC). The Centre sits under MOST's Authority of Information Technology Industry and acts as a coordinating hub between domestic chip-design firms, research institutes, and domestic / foreign fabrication and packaging partners. It provides shared EDA software access, IP libraries, technical design verification, performance measurement, training programmes, and pilot-production (MPW shuttle) support — the first concrete institutional node operationalising Vietnam's 2024 semiconductor strategy (Decision 1018/QĐ-TTg).
On 10 October 2024 the Czech government approved the National Semiconductor Strategy, prepared by the Ministry of Industry and Trade (MPO). The strategy sets five objectives to be reached by end-2029: a 300% increase in semiconductor sector sales versus 2022, a 300% increase in semiconductor component production versus 2022, a 200% increase in exports of semiconductor technologies, growth of the specialist workforce to 9,000 experts, and the build-out of a national competence centre. The strategy is positioned as the Czech implementation track for the EU Chips Act and identifies power electronics, integrated-circuit design and semiconductor manufacturing equipment as the country's competitive niches.
Law 14.968/2024 establishes the Brasil Semicon program, extending and expanding semiconductor industry incentives through 2073 (aligned with Manaus Free Trade Zone benefits). Provides R$7 billion annually in tax incentives for semiconductor and ICT sectors, with R$21 billion committed through 2026. Expands PADIS eligibility to include chip design services and software, and calculates R&D credits on total revenue rather than domestic sales alone, encouraging exports.
Uttar Pradesh notified its first dedicated state-level Semiconductor Policy on 12 February 2024 (cabinet-cleared 30 January 2024), making it the fourth Indian state with a sectoral semiconductor incentive regime after Tamil Nadu, Karnataka and Gujarat. The policy stacks a 50% additional state capital subsidy on top of the central India Semiconductor Mission (ISM) 50% subsidy — yielding an effective ~75% capex coverage for qualifying fab, display-fab, compound-semiconductor, ATMP/OSAT, and sensor units approved by ISM. It adds a 75% land rebate on the first 200 acres for ATMP/OSAT (30% on additional land), a 5% interest subsidy (capped at ₹1 cr/year for 7 years) on investments up to ₹200 cr, 100% stamp-duty and registration-fee exemption, and a 10-year electricity-duty exemption. Within months of notification the state attracted ₹40,038 cr in investment proposals (Tarq Semiconductor, Kaynes Semicon, Aditech, Vamasundari) with ~32,000 projected jobs, prompting the cabinet to later approve mega-project incentives for investments ≥ ₹3,000 cr.
The Government of Tamil Nadu released the Tamil Nadu Semiconductor and Advanced Electronics Policy 2024 at the Tamil Nadu Global Investors Meet on 7 January 2024. The policy provides a state top-up equal to 50% of the central India Semiconductor Mission (ISM) incentive for any unit approved under the central semiconductor-fab / display-fab / compound-semiconductor / ATMP / sensor / silicon photonics / discrete semiconductor schemes, plus standalone state incentives (capital subsidy, training subsidy, product testing & prototyping support, land cost concessions, stamp duty refund, electricity tax exemption, quality certification, IP, and interest subsidy). Minimum investment threshold is ₹200 crore with a minimum of 150 jobs for the initial ₹200 crore tranche; the policy is valid for three years from the date of notification and is implemented by Guidance Tamil Nadu, the state's investment-promotion agency.
The Spanish Council of Ministers approved on 24 May 2022 the Strategic Project for the Recovery and Economic Transformation of Microelectronics and Semiconductors (PERTE Chip) within the framework of the Plan de Recuperacion, Transformacion y Resiliencia (financed in large part by NextGenerationEU funds). The package commits a public envelope of roughly EUR 12.25bn through 2027 across four lines: scientific R&D capacity (~EUR 1.165bn), chip design including fabless companies (~EUR 1.330bn), manufacturing-plant construction including front-end below-5nm and above-5nm fabs (~EUR 9.350bn), and dynamisation of ICT/electronics manufacturing including a venture fund for semiconductor startups (~EUR 0.400bn). The Sociedad Espanola para la Transformacion Tecnologica (SETT), formally constituted by Real Decreto 676/2024 of 16 July 2024, is the operational vehicle managing more than EUR 10.75bn of the envelope.